Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /TIMER_CTL

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Interpret as TIMER_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PERIOD0 (SCALE)SCALE 0 (PUMP_CLOCK_SEL)PUMP_CLOCK_SEL 0 (PRE_PROG)PRE_PROG 0 (PRE_PROG_CSL)PRE_PROG_CSL 0 (PUMP_EN)PUMP_EN 0 (ACLK_EN)ACLK_EN 0 (TIMER_EN)TIMER_EN

Description

Timer control

Fields

PERIOD

Timer period in either microseconds (SCALE is ‘0’) or 100’s of microseconds (SCALE is ‘1’) multiples.

SCALE

Timer tick scale: ‘0’: 1 microsecond. ‘1’: 100 microseconds.

PUMP_CLOCK_SEL

Pump clock select: ‘0’: internal clock. ‘1’: external clock.

PRE_PROG

‘1’ during pre-program operation

PRE_PROG_CSL

‘0’ CSL lines driven by CSL_DAC ‘1’ CSL lines driven by VNEG_G

PUMP_EN

Pump enable: ‘0’: disabled ‘1’: enabled (also requires FM_CTL.IF_SEL to be ‘1’, this additional restriction is reuired to prevent non intential clearing of the FM). SW sets this field to ‘1’ to generate a single PE pulse. HW clears this field when timer is expired.

ACLK_EN

ACLK enable (generates a single cycle pulse for the FM): ‘0’: disabled ‘1’: enabled. SW set this field to ‘1’ to generate a single cycle pulse. HW sets this field to ‘0’ when the pulse is generated.

TIMER_EN

Timer enable: ‘0’: disabled ‘1’: enabled. SW sets this field to ‘1’ to start the timer. HW sets this field to ‘0’ when the timer is expired.

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